circuit Addr :
  module Addr :
    input clock : Clock
    input reset : UInt<1>
    output io : { in : { flip sf : UInt<1>, flip x : UInt<64>, flip y : UInt<64>, flip carryIn : UInt<1>}, flip calEn : { extRegEn : UInt<1>, shiftRegEn : UInt<1>, shiftInstrEn : UInt<1>, shiftRegType0 : UInt<1>, shiftRegType1 : UInt<1>, shiftRegType1Long : UInt<1>, shiftRegType2 : UInt<1>, condEn : UInt<1>, addrP0En : UInt<1>, addrP1En : UInt<1>, bitMaskEn : UInt<1>, andP0En : UInt<1>, andP1En : UInt<1>, orP0En : UInt<1>, orP1En : UInt<1>, xorP0En : UInt<1>, xorP1En : UInt<1>, movSelEn : UInt<3>, bfmEn : UInt<1>, bfmSign : UInt<1>, miscSelEn : UInt<5>}, result : UInt<64>, pstate : { n : UInt<1>, z : UInt<1>, c : UInt<1>, v : UInt<1>}}

    reg sfReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Addr.scala 32:22]
    sfReg <= io.in.sf @[Addr.scala 33:9]
    reg addrP1EnReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Addr.scala 34:28]
    addrP1EnReg <= io.calEn.addrP1En @[Addr.scala 35:15]
    node sf = mux(addrP1EnReg, sfReg, io.in.sf) @[Addr.scala 37:15]
    wire unsigned_sum : UInt<65> @[Addr.scala 39:26]
    node _unsigned_sum_T = add(io.in.x, io.in.y) @[Addr.scala 40:27]
    node _unsigned_sum_T_1 = add(_unsigned_sum_T, io.in.carryIn) @[Addr.scala 40:32]
    node _unsigned_sum_T_2 = bits(io.in.x, 31, 0) @[Addr.scala 40:45]
    node _unsigned_sum_T_3 = bits(io.in.y, 31, 0) @[Addr.scala 40:63]
    node _unsigned_sum_T_4 = add(_unsigned_sum_T_2, _unsigned_sum_T_3) @[Addr.scala 40:59]
    node _unsigned_sum_T_5 = add(_unsigned_sum_T_4, io.in.carryIn) @[Addr.scala 40:77]
    node _unsigned_sum_T_6 = mux(sf, _unsigned_sum_T_1, _unsigned_sum_T_5) @[Addr.scala 40:20]
    unsigned_sum <= _unsigned_sum_T_6 @[Addr.scala 40:15]
    wire signed_sum : SInt<65> @[Addr.scala 42:24]
    wire signed_sum_half : SInt<33> @[Addr.scala 43:29]
    node _signed_sum_T = asSInt(io.in.x) @[Addr.scala 44:19]
    node _signed_sum_T_1 = asSInt(io.in.y) @[Addr.scala 44:31]
    node _signed_sum_T_2 = add(_signed_sum_T, _signed_sum_T_1) @[Addr.scala 44:26]
    node _signed_sum_T_3 = eq(io.in.carryIn, UInt<2>("h1")) @[Addr.scala 44:49]
    node _signed_sum_T_4 = asSInt(_signed_sum_T_3) @[Addr.scala 44:62]
    node _signed_sum_T_5 = add(_signed_sum_T_2, _signed_sum_T_4) @[Addr.scala 44:38]
    signed_sum <= _signed_sum_T_5 @[Addr.scala 44:14]
    node _signed_sum_half_T = bits(io.in.x, 31, 0) @[Addr.scala 45:22]
    node _signed_sum_half_T_1 = asSInt(_signed_sum_half_T) @[Addr.scala 45:36]
    node _signed_sum_half_T_2 = bits(io.in.y, 31, 0) @[Addr.scala 45:47]
    node _signed_sum_half_T_3 = asSInt(_signed_sum_half_T_2) @[Addr.scala 45:61]
    node _signed_sum_half_T_4 = add(_signed_sum_half_T_1, _signed_sum_half_T_3) @[Addr.scala 45:43]
    node _signed_sum_half_T_5 = eq(io.in.carryIn, UInt<2>("h1")) @[Addr.scala 45:79]
    node _signed_sum_half_T_6 = asSInt(_signed_sum_half_T_5) @[Addr.scala 45:92]
    node _signed_sum_half_T_7 = add(_signed_sum_half_T_4, _signed_sum_half_T_6) @[Addr.scala 45:68]
    signed_sum_half <= _signed_sum_half_T_7 @[Addr.scala 45:18]
    node _io_result_T = bits(unsigned_sum, 63, 0) @[Addr.scala 47:34]
    node _io_result_T_1 = bits(unsigned_sum, 31, 0) @[Addr.scala 47:63]
    node _io_result_T_2 = mux(sf, _io_result_T, _io_result_T_1) @[Addr.scala 47:17]
    io.result <= _io_result_T_2 @[Addr.scala 47:12]
    node _io_pstate_c_T = bits(unsigned_sum, 64, 64) @[Addr.scala 48:36]
    node _io_pstate_c_T_1 = bits(unsigned_sum, 32, 32) @[Addr.scala 48:59]
    node _io_pstate_c_T_2 = mux(sf, _io_pstate_c_T, _io_pstate_c_T_1) @[Addr.scala 48:19]
    io.pstate.c <= _io_pstate_c_T_2 @[Addr.scala 48:14]
    node _io_pstate_n_T = bits(unsigned_sum, 63, 63) @[Addr.scala 49:36]
    node _io_pstate_n_T_1 = bits(unsigned_sum, 31, 31) @[Addr.scala 49:61]
    node _io_pstate_n_T_2 = mux(sf, _io_pstate_n_T, _io_pstate_n_T_1) @[Addr.scala 49:19]
    io.pstate.n <= _io_pstate_n_T_2 @[Addr.scala 49:14]
    node _io_pstate_z_T = bits(unsigned_sum, 63, 0) @[Addr.scala 50:36]
    node _io_pstate_z_T_1 = eq(_io_pstate_z_T, UInt<1>("h0")) @[Addr.scala 50:49]
    node _io_pstate_z_T_2 = bits(unsigned_sum, 31, 0) @[Addr.scala 50:69]
    node _io_pstate_z_T_3 = eq(_io_pstate_z_T_2, UInt<1>("h0")) @[Addr.scala 50:82]
    node _io_pstate_z_T_4 = mux(sf, _io_pstate_z_T_1, _io_pstate_z_T_3) @[Addr.scala 50:19]
    io.pstate.z <= _io_pstate_z_T_4 @[Addr.scala 50:14]
    node _io_pstate_v_T = bits(unsigned_sum, 63, 0) @[Addr.scala 51:36]
    node _io_pstate_v_T_1 = asSInt(_io_pstate_v_T) @[Addr.scala 51:50]
    node _io_pstate_v_T_2 = neq(_io_pstate_v_T_1, signed_sum) @[Addr.scala 51:56]
    node _io_pstate_v_T_3 = bits(unsigned_sum, 31, 0) @[Addr.scala 51:83]
    node _io_pstate_v_T_4 = asSInt(_io_pstate_v_T_3) @[Addr.scala 51:97]
    node _io_pstate_v_T_5 = neq(_io_pstate_v_T_4, signed_sum_half) @[Addr.scala 51:103]
    node _io_pstate_v_T_6 = mux(sf, _io_pstate_v_T_2, _io_pstate_v_T_5) @[Addr.scala 51:19]
    io.pstate.v <= _io_pstate_v_T_6 @[Addr.scala 51:14]

